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 PD- 91317C
IRLR/U2705
HEXFET(R) Power MOSFET
l l l l l l l
Logic-Level Gate Drive Ultra Low On-Resistance Surface Mount (IRLR2705) Straight Lead (IRLU2705) Advanced Process Technology Fast Switching Fully Avalanche Rated
D
VDSS = 55V
G S
RDS(on) = 0.040 ID = 28A
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications.
D-Pak TO-252AA I-Pak TO-251AA
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
28 20 110 68 0.45 16 110 16 6.8 5.0 -55 to + 175 300 (1.6mm from case )
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Case-to-Ambient (PCB mount)** Junction-to-Ambient
Typ.
--- --- ---
Max.
2.2 50 110
Units
C/W
** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994
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1
4/1/03
IRLR/U2705
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss
Min. Typ. Max. Units Conditions 55 --- --- V VGS = 0V, ID = 250A --- 0.065 --- V/C Reference to 25C, ID = 1mA --- --- 0.040 VGS = 10V, ID = 17A --- --- 0.051 W VGS = 5.0V, ID = 17A --- --- 0.065 VGS = 4.0V, ID = 14A 1.0 --- 2.0 V VDS = VGS, ID = 250A 11 --- --- S VDS = 25V, ID = 16A --- --- 25 VDS = 55V, VGS = 0V A --- --- 250 VDS = 44V, VGS = 0V, TJ = 150C --- --- 100 VGS = 16V nA --- --- -100 VGS = -16V --- --- 25 ID = 16A --- --- 5.2 nC VDS = 44V --- --- 14 VGS = 5.0V, See Fig. 6 and 13 --- 8.9 --- VDD = 28V --- 100 --- ID = 16A ns --- 21 --- RG = 6.5, VGS = 5.0V --- 29 --- RD = 1.8, See Fig. 10 Between lead, 4.5 nH 6mm (0.25in.) G from package --- 7.5 --- and center of die contact --- 880 --- VGS = 0V --- 220 --- pF VDS = 25V --- 94 --- = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 28 showing the A G integral reverse --- --- 110 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 17A, VGS = 0V --- 76 110 ns TJ = 25C, IF = 16A --- 190 290 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 ) VDD = 25V, starting TJ = 25C, L = 610H RG = 25, IAS = 16A. (See Figure 12) ISD 16A, di/dt 270A/s, VDD V(BR)DSS, TJ 175C Pulse width 300s; duty cycle 2%.
Caculated continuous current based on maximum allowable This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact. junction temperature; Package limitation current = 20A.
Uses IRLZ34N data and test conditions.
2
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IRLR/U2705
1000
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
1000
ID , Drain-to-Source Current (A)
100
ID , Drain-to-Source Current (A)
100
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
10
10
2.5V
1
1
2.5V
0.1 0.1
20s PULSE WIDTH T J = 25C
1 10
100
A
0.1 0.1
20s PULSE WIDTH T J = 175C
1 10
100
A
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = 27A
I D , Drain-to-Source Current (A)
2.5
100
TJ = 25C TJ = 175C
2.0
10
1.5
1.0
1
0.5
0.1 2 3 4 5 6
V DS = 25V 20s PULSE WIDTH
7 8 9 10
A
0.0 -60 -40 -20 0 20 40 60
VGS = 10V
80 100 120 140 160 180
A
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRLR/U2705
1400
VGS , Gate-to-Source Voltage (V)
1200
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd Ciss C oss = Cds + C gd
15
I D = 16A V DS = 44V V DS = 28V
12
C, Capacitance (pF)
1000
800
9
Coss
600
6
400
Crss
200
3
0 1 10 100
A
0 0 4 8 12 16
FOR TEST CIRCUIT SEE FIGURE 13
20 24 28 32
A
VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on)
I D , Drain Current (A)
100
100 10s
TJ = 175C TJ = 25C
10
100s 10 1ms
1 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VGS = 0V
1.8
A
1 1
TC = 25C TJ = 175C Single Pulse
10
10ms
A
100
2.0
VSD , Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRLR/U2705
30
LIMITED BY PACKAGE
25
VDS VGS RG
RD
D.U.T.
+
ID , Drain Current (A)
20
-VDD
5V
15
Pulse Width 1 s Duty Factor 0.1 %
10
Fig 10a. Switching Time Test Circuit
VDS 90%
5
0 25 50 75 100 125 150 175
TC , Case Temperature ( C)
10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
1
D = 0.50 0.20 0.10 0.05 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1
0.1
0.02 0.01
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U2705
250
EAS , Single Pulse Avalanche Energy (mJ)
TOP
200
15V
BOTTOM
ID 6.6A 11A 16A
VDS
L
DRIVER
150
RG
20V
D.U.T
IAS tp
+ V - DD
A
100
0.01
50
Fig 12a. Unclamped Inductive Test Circuit
0
VDD = 25V
25 50 75 100 125 150
A
175
V(BR)DSS tp
Starting TJ , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
10 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRLR/U2705
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
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7
IRLR/U2705
Package Outline
TO-252AA Outline Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086)
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
-B1.52 (.060) 1.15 (.045) 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) M AMB
0.58 (.023) 0.46 (.018)
2.28 (.090) 4.57 (.180)
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
Part Marking Information
TO-252AA (D-PARK)
EXAMPLE : THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 9U1P
INTERNATIONAL RECTIFIER LOGO
A
IRFR 120 9U 1P
FIRST PORTION OF PART NUMBER
ASSEMBLY LOT CODE
SECOND PORTION OF PART NUMBER
8
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IRLR/U2705
Package Outline
TO-251AA Outline Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035)
2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 6.22 (.245) 5.97 (.235)
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
3X
1.14 (.045) 0.76 (.030)
3X
0.89 (.035) 0.64 (.025) M AMB
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
2.28 (.090) 2X
0.25 (.010)
Part Marking Information
TO-251AA (I-PARK)
EXAMPLE : THIS IS AN IRFU120 WITH ASSEMBLY LOT CODE 9U1P
INTERNATIONAL RECTIFIER LOGO
IRFU 120 9U 1P
FIRST PORTION OF PART NUMBER
ASSEMBLY LOT CODE
SECOND PORTION OF PART NUMBER
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9
IRLR/U2705
Tape & Reel Information
TO-252AA Dimensions are shown in millimeters (inches)
TR TRR TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 4/03
10
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